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Naman Goyal

// I like to solve problems.

I am a third-year in Electrical Engineering at the Indian Institute of Technology Delhi, ranked first in my department. I work on quantum computing in Prof. Rajendra Kumar's group. I am an incoming Software Engineering Intern at Virtu Financial for the summer of 2027.

Previously I was a Research Intern in the Trusted Systems Group at CISPA Helmholtz Center for Information Security, where I ran a measurement study of the hardware supply chain: forensically grading 131 open-source RISC-V CPU and GPU cores against their own security claims, by reading RTL, testbenches and commit history rather than READMEs. A publication is in progress.

Outside research I build low-latency systems — execution paths in C++, data planes in FPGA fabric, and the hardware underneath them. I also compete: olympiads in physics, astronomy and mathematics, and competitive programming.

github linkedin email resume

News

  • [Aug 2026]

    Joining Virtu Financial as a Software Engineering Intern for Summer 2027.

  • [Aug 2026]

    Started research on the quantum complexity of minimum weight cycles and triangles. more

  • [Jul 2026]

    Wrapped up a research internship at CISPA Helmholtz Center on the hardware supply-chain security of open-source RISC-V cores. Publication in progress. more

  • [2026]

    Won the CISPA European AI & Cybersecurity Hackathon. more

  • [2026]

    Released a formally verified tick-to-trade engine and a wire-speed packet parser, both in SystemVerilog. more

Research

  • Quantum Complexity of Minimum Weight Cycles and Triangles

    IIT Delhi · Department of Computer Science and Engineering · 2026 – present

    Roditty and Vassilevska Williams showed that finding a minimum weight cycle in a weighted graph reduces to finding a minimum weight triangle — a classical equivalence that settled a question of Itai and Rodeh. Our goal is to understand what these problems cost on a quantum computer: which parts of that reduction survive, and what the true quantum complexity of minimum weight cycle and minimum weight triangle actually is.

  • Hardware Supply-Chain Security of Open-Source CPU & GPU Cores

    CISPA Helmholtz Center for Information Security · Trusted Systems Group · May – Jul 2026

    A large-scale measurement study of how secure open-source hardware really is. I forensically graded 131 open-source RISC-V CPU and GPU cores against their security claims — reading RTL, testbenches, and commit history rather than trusting the README.

Selected Work

  • FPGA Tick-to-Trade Pipeline 2026

    An ultra-low-latency trading system implemented entirely in FPGA fabric for wire-speed execution: hardware protocol decoding, deterministic order encoding, and fault tolerance with real-time heartbeat monitoring and corruption handling.

    code

  • Low-Latency C++ Execution Engine 2025

    A trading-style execution pipeline engineered for nanoseconds: zero-allocation architecture, lock-free SPSC ring buffers, SIMD prefetching, cache-locality tuning, and a hardware-aware scheduler with core pinning and explicit memory ordering.

    [private]

  • Wire-Speed FPGA Network Parser 2026

    A wire-speed MAC/IP/UDP header parser with a fixed-latency Level-1 trigger. Formally verified with SymbiYosys and adversarially tested with a cocotb + scapy bench that fires malformed and edge-case packets through the pipeline.

    code

all projects