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Projects

// a short list on purpose. everything else is on github.

Selected Work

  • FPGA Tick-to-Trade Pipeline

    Independent · 2026

    An ultra-low-latency trading system implemented entirely in FPGA fabric for wire-speed execution: hardware protocol decoding, deterministic order encoding, and fault tolerance with real-time heartbeat monitoring and corruption handling.

    SystemVerilog · FPGA · Formal verification · Low latency code

  • Low-Latency C++ Execution Engine

    Independent · 2025

    A trading-style execution pipeline engineered for nanoseconds: zero-allocation architecture, lock-free SPSC ring buffers, SIMD prefetching, cache-locality tuning, and a hardware-aware scheduler with core pinning and explicit memory ordering.

    C++ · Lock-free · SIMD · Low latency

  • Wire-Speed FPGA Network Parser

    Independent · 2026

    A wire-speed MAC/IP/UDP header parser with a fixed-latency Level-1 trigger. Formally verified with SymbiYosys and adversarially tested with a cocotb + scapy bench that fires malformed and edge-case packets through the pipeline.

    SystemVerilog · FPGA · SymbiYosys · cocotb code

  • Solovay–Kitaev Unitary Decomposer

    Independent · 2026

    Recursive decomposition of SU(2) unitaries into a discrete gate set at O(log^2.71(1/ε)) complexity, with a precomputed base-case table and vectorised nearest-neighbour search.

    Python · Quantum compilers · Numerical code

  • KAN-PINN Battery State-of-Health

    Independent · 2025

    A hybrid Kolmogorov–Arnold / physics-informed neural network for lithium-ion battery SOH estimation, embedding the Verhulst degradation model as a physics constraint and trained with a custom augmented-Lagrangian framework.

    PyTorch · KAN · PINN · Physics-ML code

Coursework, experiments and everything not listed here lives on github .